The present invention relates to a method of manufacturing a semiconductor device having uneven portions such as a trench capacitor and a damascene wiring, in which the particle generation causing the manufacturing yield of the semiconductor device to be lowered is suppressed by grinding or polishing the peripheral portion and beveled portion on the main surface of a target substrate such as a semiconductor substrate, and the contamination of the semiconductor substrate and the processing machine by the filled metal in the metallization trench such as a copper trench is suppressed.
With the rapid progress achieved in recent years in the degree of integration and performance of the semiconductor integrated circuit, it is of high importance to develop an SOC (System On Chip) having a DRAM (Dynamic Random Access Memory) section of a high degree of integration and a logic section formed on the same chip, said DRAM section including a trench capacitor and said logic section having a multi-layered metallization of a damascene structure in which a metal having a high electrical conductivity such as copper is buried in a wiring groove.
However, in the manufacturing process of the SOC, it is necessary to form a large number of trenches having a high aspect ratio for forming the trench capacitor in the DRAM section, and it is necessary to form a large number of wiring grooves connected to each other via contact holes having a high aspect ratio for forming a multi-layered wiring of a damascene structure in the logic section.
In the manufacturing process of an LSI having a large number of uneven portions, particularly, in forming the peripheral portion and beveled portion on the main surface of the semiconductor device, particles are generated in the process of the wafer transfer so as to lower the manufacturing yield of the semiconductor device.
It should also be noted that the metal such as copper, which is buried in the damascene wiring, degrades the semiconductor substrate and contaminates the manufacturing machine during the manufacturing process of the semiconductor device so as to greatly damage the manufacturing line of the semiconductor device.
In order to manufacture an SOC of a high degree of integration and a high performance with a high manufacturing yield, it is absolutely necessary to develop a method of suppressing the particle generation in the peripheral portion and beveled portion of semiconductor wafer with a smaller number of manufacturing steps and of suppressing the contamination with the metal such as copper buried in the damascene wiring groove. The conventional method of manufacturing a semiconductor device, which is intended to overcome the problems noted above, will now be described with reference to the accompanying drawings.
In the manufacturing process of a semiconductor device having uneven portions, the problems described in the following were generated in the peripheral portion and the beveled portion of the semiconductor wafer. The particular problems will now be described in detail, with the etching step of the trench for the trench capacitor taken as an example.
In the manufacturing process of a trench capacitor shown in FIGS. 1A to 1C, a silicon nitride film 2 and a silicon oxide film 3 are successively formed first on a silicon wafer 1 by using a hot-wall type CVD machine as shown in FIG. 1A, followed by forming a resist pattern 4 in predetermined positions of the silicon oxide film 3. It should be noted that a resist 5, which should not remain originally, remains unremoved in some cases in a peripheral portion 1a and a beveled portion 1b of the silicon wafer 1 after formation of the resist pattern 4.
In the next step, the silicon oxide film 3, the silicon nitride film 2 and the silicon wafer 1 are removed successively and selectively by an anisotropic RIE (Reactive Ion Etching) with the resist pattern 4 used as a mask so as to form a trench 6 used for forming a capacitor. In this step, the resist 5 remaining in the peripheral portion 1a and the beveled portion 1b acts as an etching mask. In addition, the material formed by the etching is attached to the peripheral portion 1a and the beveled portion 1b of the silicon wafer 1 so as to act as an etching mask. Such being the situation, an irregular uneven portion 7 is generated in the peripheral portion 1a and the beveled portion 1b of the silicon wafer 1.
The irregular uneven portion 7 also takes place in the case where the plasma in the RIE step fails to reach sufficiently the peripheral portion of the wafer so as to cause the etching of the silicon oxide film 3 and the silicon nitride film 2 to be insufficient, with the result that the remaining silicon oxide film 3 and the silicon nitride film 2 perform the function of the etching mask.
The irregular uneven portion 7 tends to be broken easily in the process of transferring the wafer to and from the wafer carrier so as to cause the particle generation and, thus, to lower the manufacturing yield of the semiconductor device. Naturally, it is necessary to remove the irregular uneven portion 7. Such being the situation, the irregular uneven portion 7 formed in the peripheral portion and the beveled portion is removed in the next step.
Specifically, the device region is protected first by forming a resist pattern 4 in a manner to cover the trench 6 formed on the main surface of the silicon wafer 1 except the peripheral portion 1a and the beveled portion 1b, as shown in FIG. 1B, followed by applying a RIE treatment under the etching conditions in which the etching selectivity ratio of the silicon oxide film 3, the silicon nitride film 2 and the silicon wafer 1 is set at 1:1:1, thereby removing the tip portion of the irregular uneven portion 7 and the upper structure.
Then, the silicon wafer exposed to the peripheral portion 1a and the beveled portion 1b is removed by a wet etching so as to smooth the surfaces of the peripheral portion 1a and the beveled portion 1b of the silicon wafer 1 as shown in FIG. 1B, followed by removing the resist pattern 4, thereby finishing the removing step of the irregular uneven portion 7.
In the subsequent step of forming a trench capacitor, an impurity is introduced into the inner wall of the trench so as to form a silicon oxynitride film as a capacitor dielectric film. Then, a polycrystalline silicon (polysilicon) film 8 forming a storage electrode is formed to fill the trench, followed by planarizing the surface of the polysilicon film 8 by a CMP (Chemical Mechanical Polishing) method, as shown in FIG. 1C.
As described above, for the removal of the irregular uneven portion, it is necessary to employ at least the four steps of the resist pattern formation, the RIE etching, the wet etching, and the removal of the resist. Naturally, the step of removing the uneven portion causes a low through-put and a high manufacturing cost and, thus, constitutes a serious problem that must be solved.
The problem generated in the edge portion of the semiconductor wafer in the process of forming a damascene wiring by using copper as a filled metal will now be described. FIGS. 2A to 2C collectively show the problem inherent in the conventional process of forming a damascene wiring by using copper.
As shown in FIG. 2A, a resist pattern (not shown) is formed on a silicon oxide film 9 after formation of the silicon oxide film 9 on a silicon wafer 1, followed by removing the silicon oxide film 9 by employing an anisotropic RIE treatment. Then, the resist pattern is removed, followed by forming a wiring trench 10 in the silicon oxide film 9. In the next step, a barrier metal (not shown) consisting of a TaN film and a Cu film is formed by means of a sputtering method, followed by depositing a Cu layer 11, which is buried in the wiring trench 10, by means of a plating method.
In the process of forming the barrier metal by the sputtering method, the TaN film and the Cu film are formed on the silicon oxide film covering the peripheral portion 1a and the beveled portion 1b of the silicon wafer 1 as well as on the inner surface of the wiring trench 10 and the upper surface of the silicon oxide film 9. Further, a Cu layer 11 is deposited on the Cu film. For the simplicity, the TaN film and the Cu film are collectively denoted as the single Cu layer 11 in FIG. 2A.
In the next step, a CMP treatment is applied to the TaN film and the Cu film formed by the sputtering method and to the Cu layer 11 formed by the plating method so as to remove the excess portions of the TaN film, the Cu film and the Cu layer 11 positioned on the silicon oxide film 9 so as to planarize the surface and, thus, to form a Cu filled metallization.
In the next step, an interlayer insulating film 12 formed of a laminate structure consisting of a silicon nitride film and a silicon oxide film is formed as shown in FIG. 2C in order to form an upper wiring layer. Incidentally, the interlayer insulating film 12 is depicted as a single insulating film in FIG. 12 for the sake of brevity.
However, since the interlayer insulating film 12 consisting of the silicon nitride film and the silicon oxide film is formed in general by using a plasma CVD method, the interlayer insulating film 12 fails to cover the entire edge portion of the silicon wafer 1, with the result that the Cu layer 11 is exposed to the edge portion of the silicon wafer 1.
It should be noted that, if the silicon wafer 1 having the Cu layer 11 exposed in the edge portion is introduced into a resist coating machine or an exposure machine in the subsequent lithography step, the Cu layer 11 exposed to the outside in the edge portion contaminates the wafer transfer system.
It should also be noted that, in the subsequent step of etching the interlayer insulating film 12 by employing an anisotropic RIE treatment using a resist pattern as a mask, the Cu layer 11 exposed to the outside in the edge portion is exposed to the plasma of RIE so as to contaminate the RIE chamber. At the same time, the silicon wafer 1 itself is contaminated with Cu.
Further, if the resist pattern is removed in the next step by using an oxygen plasma asher, the Cu layer 11 exposed to the edge portion is oxidized, with the result that the chamber of the asher and the silicon wafer 1 are contaminated with Cu. At the same time, the Cu layer 11 oxidized in the edge portion of the silicon wafer 1 is rendered brittle so as to cause a particle generation. Therefore, a serious problem is generated that the residue of the Cu layer 11 in the edge portion of the silicon wafer 1 provides a source of contamination of the processing machine and the silicon wafer. In the manufacturing process of a semiconductor device, there are various sources of contamination including, for example, PZT (Pd(Zr,Ti)O3) dielectric film in the FeRAM (Ferroelectric Random Access Memory) and the Ru stacked electrode in a stacked capacitor in addition to Cu in the damascene wiring.
As described above, at least four steps were required in the conventional process for removing the uneven portion formed in the peripheral portion and the beveled portion of the silicon wafer, leading to a long period required for the manufacture of a semiconductor device and to a high manufacturing cost.
It should also be noted that, in the manufacturing process of a damascene wiring using Cu, Cu is exposed to the edge portion of the silicon wafer. When the silicon wafer having the exposed Cu is introduced into a resist coating apparatus or a light exposure apparatus in the lithography step, a serious problem is generated that the transfer system of these apparatuses is contaminated with Cu.
Further, when the resist pattern is removed by using an etching mask in the processing of the interlayer insulating film in the upper wiring layer, the Cu exposed to the edge portion is oxidized, with the result that the chamber of the oxygen plasma asher and the silicon wafer itself are contaminated with Cu. In addition, the oxidized Cu produces a serious problem if generating particles causing a low yield.